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Featured Employers
JR0173416 - CAD Engineer Synthesis, Place and Route
Company: Intel
Location: Hudson, MA
Employment Type: Full Time
Date Posted: 09/13/2021
Expire Date: 11/12/2021
Job Categories: Computers, Software, Construction, Mining and Trades, Engineering, Healthcare, Practitioner and Technician, Information Technology, Internet/E-Commerce, Military, Research & Development, Medical, Web Technology, Energy / Utilities
Job Description
JR0173416 - CAD Engineer Synthesis, Place and Route

In this position you will be working alongside a world-class SoC System on a Chip Design team within the Xeon Performance Group, delivering next-generation Xeon products and related IPs for Server markets. You will be a key member of the design automation and methodology team and provide design enabling services to all SOCs and IPs of XEON products.

Responsibilities:

  • Develop, test, and deploy RTL2GDS tool-flow for Xeon processors using tools from multiple vendors.
  • Develop cutting edge Synthesis and Place and Route methodologies in new process nodes for external and internal foundries.
  • Enable the team in meeting the design and development targets by working closely with inhouse Design Automation experts and external tool vendors.
  • Interface between global DA experts to establish the design environment with Tools Flows Methodologies TFM on Digital Back-End domains, APRPnR, Synthesis Timing Physical and Electrical Verification LEC DRC LVS etc.
  • Coordinate with Application Engineers of multiple vendors to report and track issues gating design execution.
  • Improve the STA flow efficiency and collaborate with Global Design Automation DA expert team to drive convergence across Intel.
  • Be one point contact for bugs issues in TFM for design and development team.
  • Help the team in building PERL,TCL SKILLs scripting to ensure on quality and faster executions
  • Understand different methodologies used across different groups in Intel and industry to adopt best practices


Qualifications

Minimum Qualifications

Candidate must have Bachelors degree in Electrical/Computer Engineering and 5+ years of industry experience with: - OR - a Masters degree in Electrical/Computer Engineering and 3+ years of industry experience with:

  • VLSI design with focus in synthesis place and route skills

  • RTL2GDS including Floorplanning synthesis place route clock construction

  • PPA Power Performance Area Optimization

  • Layout timing LEC verification

  • TCL Python PERL and other scripting languages

2+ years of experience in one or more of these tools:

  • Design Compiler, IC Complier, Fusion Complier, Cadence synthesis APR tool 

Preferred Qualifications

Experience with:

  • Physical aspect of VLSI designs

Inside this Business Group

Xeon Performance Group (XPG) delivers custom server SoC design solutions to our data center customers. It is chartered to deliver data centric silicon that is high-performing, cost-effective, high-quality, and on schedule in way that increases market share and drives the best solutions for our customers.



Other Locations

US, California, Santa Clara;US, Colorado, Fort Collins



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$111,000.00-$166,390.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
USExperienced HireJR0173416HudsonXeon Performance Group (XPG)
Contact Information
Company Name: Intel
Website: http://www.applytracking.com/x.aspx...
Company Description:

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